VLSI Projects list | VLSI Projects Ideas | Projects Based On VLSI

VLSI Projects list | VLSI Projects Ideas | Projects Based On VLSI

latest IEEE VLSI Projects for engineering student,projects based on vlsi.also large collection of  project topics based on vlsi technology

• Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits
• Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder
• Design of Low Power High Speed VLSI Adder Subsystem
• Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
• Synthesis and Implementation of UART using VHDL Codes
• Hardware Algorithm for Variable Precision Multiplication on FPGA
• HICPA: A Hybrid Low Power Adder for High-Performance Processors
• BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
• Low-Power and Area-Efficient Carry Select Adder
• An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation With Rf Output for SDR

VLSI PROJECTS LIST 2013

• Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
• A VLSI-BASED ROBOT DYNAMICS LEARNING ALGORITHM
• Design and Implementation of a High Performance Multiplier using HDL
• A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
• Design of Low-Power and High Performance Radix-4 Multiplier
• A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
• Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
• Simulation Based Edge Detection.
• FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers
• FPGA Implementation(s) of a Scalable Encryption Algorithm.
• High Speed and Area Efficient Vedic Multiplier
• Fpga Based Power Efficient Channelizer for Software Defined Radio
• High speed Modified Booth Encoder multiplier for signed and unsigned numbers
• Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
• An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
• Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
• High Speed Signed Multiplier for Digital Signal Processing Applications
• An Fpga-Based Architecture for Real Time Image Feature Extraction
• Accumulator Based 3-Weight Pattern Generation
• Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA
• Design of Low Power TPG Using LP-LFSR
• Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications
• Viterbi-Based Efficient Test Data Compression
• On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
• A Feature-Based Robust Digital Image Watermarking Scheme
• A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems
• Digital Image Watermarking Based on Super Resolution Image Reconstruction
• Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power
• Hardware Implementation of a Digital Watermarking System for Video Authentication
• Design Of Reconfigurable Coprocessor for Communication Systems
• Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code
• DMA Controller (Direct Memory Access ) Using VHDL/VLSI
• Watermarking Scheme for Copyright Protection of 3d Animated Model
• Edge detection using VHDL
• Efficiency of BCH Codes in Digital Image Watermarking
• Area-Efficient Universal Cryptography Processor for Smart Cards

VLSI BASED PROJECTS IDEAS

• Image Magnification by Modifying DCT Coefficients
• The CSI Multimedia Architecture
• A Real-time Face Detection And Recognition System
• VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn
• VHDL Implementation of UART with Status Register
• Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation
• Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC
• A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications
• FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
• Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application
• Pipelined Parallel FFT Architectures via Folding Transformation
• Implementation of IEEE 802.11 a Wlan Baseband Processor
• VHDL Design for Image Segmentation using Gabor filter for Disease Detection.
• A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
• An Efficient Viterbi Decoder
• A Verilog Implementation of UART Design with Bist Capability
• Improved Architectures for a Fused Floating-Point Add-Subtract Unit
• A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance
• Very Low Resolution Face Recognition Problem
• Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications
• Improved Architectures for a Fused Floating-Point Add-Subtract Unit
• A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
• Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
• A Low-Power Multiplier With The Spurious Power Suppression Technique